The present invention relates to a semiconductor device incorporated with a capacitance element having a dielectric layer of a high dielectric constant, and a manufacturing method of the same.
The advancement of information and communication field requires large capacity data to be processed at a high speed. For realizing this request, more dense integration in semiconductor integrated circuit such as semiconductor memories is in progress. Also, reducing a chip space as well as a number of parts through more dense integration is promoted.
In this background, a technique to form capacitance elements using metal oxide dielectric materials having high dielectric constants in the semiconductor integrated circuit has been positively studied in recent years. The metal oxide dielectric materials having high dielectric constants include barium titanate (BTO), strontium titanate (STO), lead titanate zirconate (PZT). These dielectric materials have dielectric constants ranging as much as a few dozen to several hundreds times of those of silicon oxide and silicon nitride which are conventional dielectric materials for the capacitance elements incorporated in integrated circuits. Forming the capacitance element which uses a dielectric material of a high dielectric constant can substantially reduce an area occupied by the capacitance element in the integrated circuit comparing with the capacitance element using the conventional materials. As a result, more dense integration is achieved.
When incorporating the capacitance element which uses a ferroelectric layer such as PZT, a nonvolatile memory can be designed because such capacitance element has spontaneous polarization. For the spontaneous polarization remains even if applied electric field is removed, and thus, a memorized content will not be lost when being powered off.
A semiconductor device incorporated with the capacitance element using ferroelectric such as a semiconductor memory device is generally manufactured as follows:
First, form an isolation oxide layer on a silicon substrate, and then form a MOS transistor comprising a diffusion layer, gate insulating layer, and gate electrode. Next, form an interlayer insulating layer covering both the MOS transistor and isolation oxide layer, then form an capacitance element on the interlayer insulating layer. The capacitance element comprises three consecutive layers fabricated, namely, a lower electrode, ferroelectric layer, and upper electrode. After the capacitance element is formed, heat treatment is provided in the oxygen atmosphere where temperature ranges from 600.degree. C. to 900.degree. C. in order to improve the crystallinity by accelerating the sintering of ferroelectric layer upon necessity. PA1 Second, cover the interlayer insulating layer including the capacitance element with a passivation layer, and then form first and second contact holes. The first contact holes lead to the diffusion layer passing through both the interlayer insulating layer and passivation layer. The second contact holes lead respectively to the lower and upper electrodes of the capacitance element passing through the passivation layer. PA1 Third, form interconnections some of which touch the diffusion layer through the first contact holes as well as the other touch the lower and upper electrodes through the second contact holes. PA1 (1) a semiconductor substrate on whose surface an integrated circuit is formed, PA1 (2) a first insulating layer formed on the semiconductor substrate, PA1 (3) a capacitance element formed on the first insulating layer, and PA1 (4) a second insulating layer formed on the first insulating layer to cover the capacitance element. PA1 (a) forming a first insulating layer on a surface of semiconductor substrate on which an integrated circuit is formed, PA1 (b) forming a capacitance element which uses a dielectric layer having a high dielectric constant on the first insulating layer, PA1 (c) forming a second insulating layer to cover the capacitance element on the first insulating layer, PA1 (d) forming first contact holes in the first and second insulating layers to lead to the integrated circuit in the first and second insulating layers, PA1 (e) forming second contact holes in the second insulating layer to lead to respectively a lower and an upper electrodes of the capacitance element, PA1 (f) annealing a dielectric material in hydrogen gas or mixed gas of hydrogen with inert gas at a temperature ranging from 350.degree. C. to 500.degree. C., PA1 (g) dehydrogenation treatment, after the annealing step, in any one of gases of oxygen, inert gas, and mixed gas of oxygen with inert gas at a temperature raging from 300.degree. C. to 450.degree. C., and PA1 (h) forming interconnections which are connected to the integrated circuit and capacitance element passing through the first and second contact holes. PA1 (a) Schottky barrier height of the interfaces between the upper and lower electrodes and the dielectric layer heightens in response to the decrease of hydrogen density. PA1 (b) A grain boundary potential height heightens in response to the decrease of hydrogen density.
The characteristics of semiconductor is deteriorated in the semiconductor memory device thus produced which is incorporated with the capacitance element using a metal-oxide-dielectric material, because oxygen reaches to the MOS transistor during the high-temperature heat treatment, and the surface state density increases on silicon interface.
The life of semiconductor memory devices using such dielectric materials is not always long enough. The reason is that the dielectric layer absorbs hydrogen. In general, when applying electric field to a capacitor made from a metal-oxide-dielectric material containing hydrogen gas, the hydrogen moves to form space charges. Therefore, when application of electric field is repeated, dielectric characteristic is deteriorated, which shortens the life of capacitor. A countermeasure to this deteriorating of dielectric characteristic is proposed: Emit hydrogen from a dielectric material by annealing the dielectric material in inert gas or vacuum at 500.degree. C. or higher temperature.
However, when this annealing method is applied to the above semiconductor memory device, the capacitance element has a large leakage current, and the life characteristic is not always improved.